Team develops silicon photonic MEMS compatible with semiconductor manufacturing
. While in principle, power consumption is only required for charging the capacitor, leak currents and power supplies do contribute to the system level power consumption in the steady state. Here, MEMS can provide an additional unique capability to exhibit no power consumption in the steady state by exploiting latching mechanisms.
The demonstrated devices represent examples of a versatile and powerful silicon photonics platform extension with MEMS. The potential of this technology extends far beyond our selected demonstrations. Namely, we predict that a myriad of devices can be implemented in standardized silicon photonic MEMS, including microphones, optomechanical sensors, spectrometers, accelerometers, pressure sensors, Brillouin scattering-based sensors, etc.
This unique combination fulfils the requirements of scalability and provides outstanding potential for the integration of MEMS in very large-scale photonic integrated circuits. For example, our phase shifters and tunable couplers constitute an elementary basis for integrated linear optics, and our switches and tunable filters underline the potential for applications in telecommunications, for example, in wavelength-selective switches.
Individual devices are arranged and placed on the chip for immediate testing in the lab following MEMS release. Larger-scale circuits consist of several such devices connected to one another. These circuits not only take up more real estate on the chip and must therefore be strategically placed but must also undergo additional electrical and optical packaging before testing because of the large number of contacts and inputs/outputs.
shows both the layout and a microscope image of the full chip, indicating regions that have been allocated for individual device testing, as well as those reserved for particular multicomponent functions, e.g., switch matrices and beam shaping.Layout of the full silicon photonics chip provided for fabrication at IMEC. Regions highlighted in green indicate the portions of the chip allocated to the testing of new geometries, functionalities, etc., at the individual device level.
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